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VCD dumping in Chisel 6.5 / svsim
By admin | November 1, 2024
Since Chisel 5, chiseltest (formerly known as chisel-testers2) is no longer supported and has been replaced with svsim in the default chisel-template. Unfortunately, the new system doesn’t provide an easy way to dump VCDs from tests.
On vanilla Chisel 6.5 this ended up requiring two separate hacks against EphemeralSimulator
:
- https://github.com/edwardcwang/decoupled-serializer/blob/master/src/main/scala/VCDHackedEphemeralSimulator.scala#L44
InsertingtraceStyle = Some(verilator.Backend.CompilationSettings.TraceStyle.Vcd(traceUnderscore = true))
into thebackendSpecificCompilationSettings
of theDefaultSimulator
. - https://github.com/edwardcwang/decoupled-serializer/blob/master/src/main/scala/VCDHackedEphemeralSimulator.scala#L31
The above was not enough as it added support for tracing but did not actually call the functions to enable & start the dumping.
Hacking thesimulate()
method to insert a call tomodule.controller.setTraceEnabled(true)
to actually enable the dump of the.vcd
file.
Third bonus hack: use the local test_run_dir
directory (from older versions of Chisel) instead of a temporary one which gets deleted.
https://github.com/edwardcwang/decoupled-serializer/blob/master/src/main/scala/VCDHackedEphemeralSimulator.scala#L61
See also:
https://github.com/chipsalliance/chisel/issues/4246
https://github.com/chipsalliance/chisel/issues/4203
https://github.com/chipsalliance/chisel/discussions/3957
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